EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 263

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 7–29. Stratix III mini-LVDS I/O Standard Termination
Note to
(1)
Altera Corporation
November 2007
Termination
Termination
On-Board
External
OCT
The R
Figure
S
and R
7–29:
Transmitter
Transmitter
P
f
values are pending characterization.
One-Resistor Network (mini-LVDS_E_1R)
≤1 inch
≤1 inch
For more information the RSDS I/O standard, refer to the RSDS
Specification from the National Semiconductor web site at
www.national.com.
mini-LVDS
Stratix III devices support the mini-LVDS output standard with a data
rate up to 340 Mbps using LVDS output buffer types. For transmitters,
use the two single-ended output buffers with the external one- or
three-resistor network, as shown in
topology is for a data rate of up to 200 Mbps. The three-resistor topology
is for a data rate of higher than 200 Mbps. The row I/O banks support
mini-LVDS output using dedicated LVDS output buffers without an
external resistor network.
A resistor network is required to attenuate the LVDS output voltage
swing to meet the mini-LVDS specifications. You can modify the
three-resistor network values to reduce power or improve the noise
margin. The resistor values chosen should satisfy the following equation:
R
R
P
P
50 Ω
50 Ω
50 Ω
50 Ω
100 Ω
100 Ω
Stratix III OCT
Receiver
Receiver
Note (1)
Transmitter
Transmitter
Figure
Stratix III Device Handbook, Volume 1
Three-Resistor Network (mini-LVDS_E_3R)
R S
R S
≤1 inch
≤
R S
R S
1 inch
7–29. The one-resistor
R
P
Stratix III Device I/O Features
R
P
50 Ω
50 Ω
50 Ω
50 Ω
100 Ω
100
Ω
Stratix III OCT
Receiver
Receiver
7–45