EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 52

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Adaptive Logic Modules
Figure 2–14. Example of a 3-Bit Add Utilizing Shared Arithmetic Mode
2–18
Stratix III Device Handbook, Volume 1
3-Bit Add Example
3-Bit Add Example
1
1
in LUTs.
in LUTs.
2
2
in s.
in s.
st
st
nd
nd
stage add is implemented
stage add is implemented
stage add is implemented
stage add is implemented
+ 1 1 0 0
1 1 1 1 1
+ 1 1 0 1
Binary Add
0 1 1 1
1 1 1 0
0 1 0 0
+ C3 C2 C1 C0
+ 2 x 12
Decimal
Equivalents
+
R4 R3 R2 R1 R0
+ 13
An example of a three-bit add operation utilizing the shared arithmetic
mode is shown in
carry (C[3..0]) is obtained using the LUTs, while the result (R[3..0]) is
computed using the dedicated adders.
Shared Arithmetic Chain
The shared arithmetic chain available in enhanced arithmetic mode
allows the ALM to implement a three-input add. This significantly
reduces the resources necessary to implement large adder trees or
correlator functions.
The shared arithmetic chains can begin in either the first or sixth ALM in
an LAB. The Quartus II Compiler creates shared arithmetic chains longer
than 20 (10 ALMs in arithmetic or shared arithmetic mode) by linking
X3 X2 X1 X0
Y3 Y2 Y1 Y0
S3 S2 S1 S0
14
Z3 Z2 Z1 Z0
31
7
4
Figure
2–14. The partial sum (S[3..0]) and the partial
X3
Y3
Z3
X0
Y0
X1
Y1
X2
Y2
Z0
Z1
Z2
ALM Implementation
ALM 1
ALM 2
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
3-Input
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
S0
C0
S1
C1
S2
C2
S3
C3
shared_arith_in = '0'
Altera Corporation
carry_in = '0'
October 2007
R2
R3
R4
R0
R1