EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 233

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 7–8. Stratix III IOE Structure
Notes to
(1)
(2)
Altera Corporation
November 2007
Firm Core
D3_0 and D3_1 delays have the same available settings in the Quartus
One dynamic OCT control is available per DQ/DQS group.
DQS
CQn
OE
from
Core
Write
Data
from
Core
clkout
To
Core
To
Core
Read
Data
to
Core
clkin
Figure
4
4
D4 Delay
7–8:
2
Rate Block
Half Data
f
Rate Block
Half Data
Rate Block
Half Data
Delay
D3_1
Synchronization
Alignment and
Registers
The output and OE paths are divided into output or OE registers,
alignment registers, and HDR blocks. You can bypass each block of the
output and output-enable path.
For more information about I/O registers and how they are used for
memory applications, refer to the
Devices
3.3-V I/O Interface
Stratix III I/O buffers are fully compatible with 3.3-V I/O standards and
you can use them as transmitters or receivers in your system. The output
high voltage (V
Alignment
Alignment
Registers
Registers
Notes
chapter in volume 1 of the Stratix III Device Handbook.
Output Register
Output Register
OE Register
OE Register
D
D
D
D
PRN
PRN
PRN
PRN
(1),
Q
Q
Q
Q
(2)
OH
), output low voltage (V
Delay
Delay
D3_0
D1
Input Register
Input Register
D
D
PRN
PRN
D5, D6
Delay
Q
Q
D2 Delay
Programmable
Input Register
Strength and
D
Slew Rate
Current
Control
PRN
External Memory Interfaces in Stratix III
Q
®
Open Drain
Stratix III Device Handbook, Volume 1
II software.
D5, D6
Delay
Output Buffer
OL
Input Buffer
), input high voltage (V
Stratix III Device I/O Features
PCI Clamp
DQS Logic Block
V CCIO
D5_OCT
Dynamic OCT Control (2)
V CCIO
Pull-Up Resistor
Programmable
Termination
Calibration
From OCT
On-Chip
Bus-Hold
Block
D6_OCT
Circuit
IH
7–15
),