EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 178

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
Figure 6–19. External Clock Outputs for Left/Right PLLs
Notes to
(1)
(2)
(3)
6–28
Stratix III Device Handbook, Volume 1
These clock output pins can be fed by any one of the C[6..0], m counters.
The CLKOUT0p and CLKOUT0n pins are dual-purpose I/O pins that can be used as two single-ended outputs or one
single-ended output and one external feedback input pin.
These external clock enable signals are available only when using the altclkctrl megafunction.
Figure
6–19:
f
LEFT/RIGHT
PLL_<L2, L3, R2, R3>_FB0/CLKOUT0p (1), (2)
Each pin of a single-ended output pair can either be in-phase or
180-degrees out-of-phase. The Quartus II software places the NOT gate in
the design into the IOE to implement 180 phase with respect to the other
pin in the pair. The clock output pin pairs support the same I/O
standards as standard output pins (in the top and bottom banks) as well
as LVDS, LVPECL, differential HSTL, and differential SSTL.
Refer to the
Stratix III Device Handbook to determine which I/O standards are
supported by the PLL clock input and output pins.
Stratix III PLLs can also drive out to any regular I/O pin through the
global or regional clock network. You can also use the external clock
output pins as user I/O pins if external PLL clocking is not needed.
Stratix III PLL Software Overview
Stratix III PLLs are enabled in the Quartus II software by using the altpll
megafunction.
named in the altpll megafunction of the Quartus II software.
PLLs
clkena0 (3)
m(fbout)
clkena1 (3)
Stratix III Device I/O Features
C0
C1
C2
C3
C4
C5
C6
PLL_<L2, L3, R2, R3>_FB1/CLKOUT0n (1), (2)
Figure 6–20
shows the Stratix III PLL ports as they are
Internal Logic
chapter in volume 1 of the
Altera Corporation
November 2007