EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 486

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Error Detection Timing
15–12
Stratix III Device Handbook, Volume 1
the error detection clock frequency.
minimum interval time between each update for the Error Message
Register for Stratix III devices.
Software Support
The Quartus II software, starting with version 6.1, supports the error
detection CRC feature for Stratix III devices. Enabling this feature
generates the CRC_ERROR output to the optional dual purpose
CRC_ERROR pin.
The error detection CRC feature is controlled by the Device and Pin
Options dialog box in the Quartus II software.
Enable the error detection feature using CRC by performing the
following steps:
1.
2.
3.
4.
Note to
(1)
Table 15–7. Minimum Update Interval for Error Message Register
Open the Quartus II software and load a project using a Stratix III
device.
On the Assignments menu, click Settings. The Settings dialog box
is shown.
In the Category list, select Device. The Device page is shown.
Click Device and Pin Options. The Device and Pin Options dialog
box is shown (see
These timing numbers are preliminary.
Table
EP3SE260
EP3SE110
EP3SL110
EP3SL150
EP3SL200
EP3SL340
15–7:
EP3SE50
EP3SE80
EP3SL50
EP3SL70
Device
Figure
15–3).
Table 15–7
Timing Interval (μs)
shows the estimated
11
11
16
16
17
21
23
11
16
16
Altera Corporation
October 2007
Note (1)