EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 289

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
is valid. If the DM/BWSn signal is high, the memory will mask the DQ
signals. If the system does not require write data masking, connect the
memory DM pins low to indicate every write data is valid. You can use
any of the DQ pins in the same DQS/DQ group as write data for the
DM/BWSn signals. Each group of DQS and DQ signals in DDR3, DDR2,
and DDR SDRAM devices requires a DM pin. There is one DM pin per
RLDRAM II device and one BWSn pin per nine bits of data in ×9, ×18, and
×36 QDRII+/QDRII SRAM. The ×8 QDRII SRAM device has 2 BWSn pins
per 8 data bits, which are referred to as the NWSn pins. Generate the DM
or BWSn signals using DQ pins and configure the signals similarly to the
DQ (or D) output signals. Stratix III devices do not support the DM signal
in ×4 DDR3 SDRAM or in ×4 DDR2 SDRAM interfaces with differential
DQS signaling.
Some DDR3, DDR2, and DDR SDRAM devices or modules support error
correction coding (ECC), which is a method of detecting and
automatically correcting errors in data transmission. In a 72-bit DDR3,
DDR2, or DDR SDRAM interface, typically eight ECC pins are used in
addition to the 64 data pins. Connect the DDR3, DDR2, and DDR SDRAM
ECC pins to a Stratix III device DQS/DQ group. These signals are also
generated like DQ pins. The memory controller needs encoding and
decoding logic for the ECC data. Designers can also use the extra byte of
data for other error checking methods.
QVLD pins are used in RLDRAM II and QDRII+ SRAM interfaces to
indicate the read data availability. There is one QVLD pin per memory
device. A high on QVLD indicates that the memory is outputting the data
requested. Similar to DQ inputs, this signal is edge-aligned with the read
clock signals (CQ/CQn in QDRII+/QDRII SRAM and QK/QK# in
RLDRAM II) and is sent half a clock cycle before data starts coming out
of the memory. The QVLD pin is not used in the ALTMEMPHY solution
for QDRII+ SRAM.
Refer to the
more information on the parity, ECC, and QVLD pins as these pins are
treated as DQ pins.
Address and Control/Command Pins
Address and control/command signals are typically sent at single data
rate. The only exception is in QDRII SRAM burst-of-two devices, where
the read address needs to be captured on the rising edge of the clock
while the write address needs to be captured on the falling edge of the
clock by the memory. There is no special circuitry required for the
address and control/command pins. You can use any of the user I/O pins
in the same I/O bank as the data pins.
“Data and Data Clock/Strobe Pins”
External Memory Interfaces in Stratix III Devices
Stratix III Device Handbook, Volume 1
section on
page 8–6
8–19
for