EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 371

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
Figure 11–3. Single Device FPP Configuration Using an External Host
Note to
(1)
Upon power-up, the Stratix III device goes through a POR. The POR
delay is dependent on the PORSEL pin setting. When PORSEL is driven
low, the POR time is approximately 100 ms. When PORSEL is driven
high, the POR time is approximately 12 ms. During POR, the device
resets, holds nSTATUS low, and tri-states all user I/O pins. Once the
device successfully exits POR, all user I/O pins continue to be tri-stated.
If nIO_pullup is driven low during power up and configuration, the
user I/O pins and dual-purpose I/O pins have weak pull-up resistors,
which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in the
reset stage. To initiate configuration, the MAX II device must drive the
nCONFIG pin from low to high.
1
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ
pull-up resistor. Once nSTATUS is released, the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the MAX II device places the configuration data one byte at
a time on the DATA[7..0] pins.
(MAX II Device or
Microprocessor)
You should connect the resistor to a supply that provides an acceptable input
signal for the device. V
the I/O on the device and the external host.
External Host
ADDR DATA[7..0]
Figure
V
configuration and JTAG pins reside need to be fully powered to
the appropriate voltage levels in order to begin the
configuration process.
Memory
CC
, V
11–3:
CCIO
, V
CCPGM
CC
should be high enough to meet the V
, and V
10 kΩ
V
CC
(1)
CCPD
Stratix III Device Handbook, Volume 1
V
CC
of the banks where the
10 kΩ
GND
(1)
Configuring Stratix III Devices
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Stratix III Device
IH
MSEL[2..0]
specification of
nCEO
11–11
GND
N.C.