EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 95

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 4–15. Stratix III Read-During-Write Data Flow
Altera Corporation
November 2007
f
Port A
data in
Port A
data out
For more information on register packing, see the
Adaptive Logic Modules in Stratix III Devices
Stratix III Device Handbook.
Conflict Resolution
When using the memory blocks in true dual-port mode, it is possible to
attempt two write operations to the same memory location (address).
Since no conflict resolution circuitry is built into the memory blocks, this
results in unknown data being written to that location. Therefore, you
must implement conflict resolution logic external to the memory block to
avoid address conflicts.
Read During Write
You can customize the read-during-write behavior of the Stratix III
TriMatrix memory blocks to suit your design needs. Two types of
read-during-write operations are available: same port and mixed port.
Figure 4–15
Same-Port Read-During-Write Mode
This mode applies to either a single-port RAM or the same port of a true
dual-port RAM. In same-port read-during-write mode, three output
choices are available: new data mode (or flow-through), old data mode,
or don't care mode. In new data mode, the new data is available on the
rising edge of the same clock cycle on which it was written. In old data
shows the difference between the two types.
TriMatrix Embedded Memory Blocks in Stratix III Devices
Port B
data in
Port B
data out
Stratix III Device Handbook, Volume 1
chapter in volume 1 of the
Logic Array Blocks and
Mixed-port
data flow
Same-port
data flow
4–21