EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 275

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 8–2. External Memory Interface Data Path Overview
Note to
(1)
(2)
Altera Corporation
November 2007
Clock Management & Reset
Each register block can be bypassed.
The blocks for each memory interface may differ slightly.
Figure
8–2:
Resynchronization Clock
DQ Write Clock
Half-Rate Clock
Alignment Clock
DQS Write Clock
Half-Rate
Figure 8–2
uses all the Stratix III IOE features.
This chapter describes the hardware features in Stratix III devices that
facilitate high-speed memory interfacing for each DDR memory
standard. Stratix III devices feature DLLs, PLLs, dynamic OCT,
read/write leveling, and deskew ciruitry.
FIFO
(2)
4n
4
4n
shows the overview of the memory interface data path that
Output Registers
Output Registers
Half Data Rate
Half Data Rate
Half Data Rate
Input Registers
2n
2
2n
External Memory Interfaces in Stratix III Devices
Synchronization
Alignment &
Resynchronization Clock
Alignment
Alignment
Registers
Registers
Registers
Note
DLL
(1),
2n
Stratix III Device Handbook, Volume 1
2
2n
(2)
DQS Logic
DDR Output
Registers
DDR Output
Registers
DDR Input
Registers
Block
Stratix III FPGA
n
n
Memory
DQS (Read)
DQ (Read)
DQ (Write)
DQS (Write)
8–5