EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 337

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Differential Pin
Placement
Guidelines
Altera Corporation
November 2007
To ensure proper high-speed operation, differential pin placement
guidelines have been established. The Quartus II compiler automatically
checks that these guidelines are followed and issues an error message if
they are not met.
Since DPA usage adds some constraints on the placement of high-speed
differential channels, this section is divided into pin placement guidelines
with and without DPA usage.
Guidelines for DPA-Enabled Differential Channels
The Stratix III device has differential receivers and transmitters in I/O
banks on the left and right sides of the device. Each receiver has a
dedicated DPA circuit to align the phase of the clock to the data phase of
its associated channel. When DPA-enabled channels are used in
differential banks, you must adhere to the guidelines listed in the
following sections.
DPA-Enabled Channels and Single-Ended I/Os
When there is a DPA channel enabled in a bank, both single-ended I/Os
and differential I/O standards are allowed in the bank.
■
■
■
Single-ended I/Os are allowed in the same I/O bank as long as the
single-ended I/O standard uses the same VCCIO as the
DPA-enabled differential I/O bank.
Single-ended inputs can be in the same LAB row as a differential
channel using the SERDES circuitry; however, IOE input registers
are not available for the single-ended I/Os placed in the same LAB
row as differential I/Os. The same rule for input registers applies for
non-SERDES differential inputs placed within the same LAB row as
a SERDES differential channel. The input register must be
implemented within the core logic.
Single-ended output pins must be at least one LAB row away from
differential I/O pins, as shown in
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
Stratix III Device Handbook, Volume 1
Figure
9–18.
9–21