EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 692

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
1–180
Stratix III Device Handbook, Volume 2
RCLK output adder
RCLK PLL output adder
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
3.3-V LVTTL
Table 1–83. EP3SL150 Column Pin Delay Adders for Regional Clock
Table 1–84. EP3SL150 Row Pin Delay Adders for Regional Clock
Table 1–85. EP3SL200 Column Pins Input Timing Parameters (Part 1 of 4)
I/O Standard
Parameter
Parameter
GCLK
GCLK
Clock
PLL
Table 1–84
Regional Clock.
EP3SL200 I/O Timing Parameters
Table 1–85
parameters for EP3SL200 devices for single-ended I/O standards.
Table 1–85
single-ended I/O standards.
Industrial
Industrial
Parameter
—
—
—
—
—
—
t
t
t
t
SU
SU
Fast Model
H
H
Fast Model
specifies EP3SL200 Column Pins Input Timing parameters for
specifies EP3SL150 Row Pin delay adders when using the
through
Commercial
Commercial
Industrial Commercial
0.025
0.003
-0.061
-0.043
1.729
1.749
—
—
—
—
Table 1–88
Fast Model
V
0.104
0.085
1.1V
-1.166
-0.392
CCL
1.274
0.500
-2
-0.015 0.056
2.634
2.658
0.011
V
show the maximum I/O timing
1.1V
CCL
-2
=
=
V
0.179
0.131
1.1V
CCL
-3
V
2.894
2.915
0.086
1.1V
CCL
-3
=
-1.691 -1.810 -1.943 -1.874 -2.327
-0.777 -0.913 -1.037 -0.978 -0.865
V
1.833
0.919
1.1V
=
CCL
-2
0.288
0.236
V
1.1V
=
CCL
-4
3.175
3.248
0.168
0.138
V
1.1V
CCL
-4
=
V
1.971
1.074
1.1V
=
CCL
-3
V
0.242
0.192
1.1V
=
-4L
CCL
V
3.035
3.108
0.112
1.1V
0.18
CCL
Altera Corporation
=
2.118
1.212
V
1.1V
=
CCL
-4L
-4
November 2007
V
0.452
0.453
0.9V
=
-4L
V
2.871
2.903
0.329
CCL
0.9V
0.46
CCL
=
V
2.041
1.145
=
1.1V
CCL
Units
=
Units
ns
ns
-4L
ns
ns
ns
ns
V
2.488
1.026
0.9V
CCL
=
Units
ns
ns
ns
ns