EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 397

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 11–16. PS Configuration Timing Waveform
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
November 2007
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix III device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
You should not leave DCLK floating after configuration. You should drive it high or low, whichever is more
convenient. DATA[0] is available as a user I/O pin after configuration. The state of this pin depends on the
dual-purpose pin settings.
CONF_DONE (3)
Figure
nSTATUS (2)
INIT_DONE
nCONFIG
11–16:
User I/O
DCLK
DATA
f
t
t
CF2CD
CFG
t
You can use a single configuration chain to configure Stratix III devices
with other Altera devices. To ensure that all devices in the chain complete
configuration at the same time, or that an error flagged by one device
initiates reconfiguration in all devices, all of the device CONF_DONE and
nSTATUS pins must be tied together.
For more information on configuring multiple Altera devices in the same
configuration chain, refer to the
chapter in the Configuration Handbook.
PS Configuration Timing
Figure 11–16
using a MAX II device as an external host.
CF2ST1
t
CF2ST0
t
CF2CK
t
ST2CK
t
Bit 0 Bit 1 Bit 2 Bit 3
STATUS
High-Z
t
CH
t
CLK
t
DSU
t
CL
t
DH
shows the timing waveform for PS configuration when
(1)
Configuring Mixed Altera FPGA Chains
Bit n
Stratix III Device Handbook, Volume 1
Configuring Stratix III Devices
t
CD2UM
User Mode
(4)
(4)
11–37