EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 186

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
Figure 6–24. Zero-Delay Buffer Mode in Stratix III PLLs
6–36
Stratix III Device Handbook, Volume 1
inclk
÷n
Figure 6–25
relationship in ZDB mode.
Figure 6–25. Phase Relationship Between PLL Clocks in Zero Delay Buffer
Mode
Note to
(1)
External Feedback Mode
In external-feedback (EFB) mode, the external-feedback input pin (fbin)
is phase-aligned with the clock input pin, as shown in
Aligning these clocks allows you to remove clock delay and skew
between devices. This mode is supported on all Stratix III PLLs.
Register Clock Port
PFD
The internal PLL clock output can lead or lag the external PLL clock outputs.
Clock Outputs (1)
PLL Clock at the
Dedicated PLL
Figure
CP/LF
PLL Reference
Clock at the
Input Pin
shows an example waveform of the PLL clocks' phase
6–25:
VCO
Phase Aligned
÷C0
÷C1
÷m
fbout
fbin
PLL_<#>_CLKOUT#
PLL_<#>_CLKOUT#
Figure
Altera Corporation
bi-directional
I/O pin
November 2007
6–27.