EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 567

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
Table 1–45. EP3SL50 Column Pins Input Timing Parameters (Part 1 of 4)
I/O Standard
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
User I/O Pin Timing
Table 1–45
devices. I/O buffer t
clock is driven by a non-PLL global clock (GCLK) and a PLL driven global
clock (GCLK-PLL). For t
from the adder tables listed for each device to the GCLK/GCLK-PLL
values for the device.
EP3SL50 I/O Timing Parameters
Table 1–45
parameters for EP3SL50 devices for single-ended I/O standards.
Table 1–45
single-ended I/O standards.
Parameter
t
t
t
t
t
t
t
t
SU
t
SU
t
SU
t
SU
t
SU
t
SU
t
SU
t
SU
t
H
H
H
H
H
H
H
H
through
through
specifies EP3SL50 Column Pins Input Timing parameters for
Industrial Commercial
Stratix III Device Datasheet: DC and Switching Characteristics
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Fast Model
Table 1–144
Table 1–48
SU
, t
SU
H
-0.721
-0.336
-0.721
-0.336
-0.721
-0.336
-0.721
-0.336
, and t
0.829
0.444
0.829
0.444
0.829
0.444
0.829
0.444
, t
H
and t
show the maximum I/O timing
show user I/O pin timing for Stratix III
CO
CO
are reported for the cases when I/O
-1.039 -1.108 -1.177 -1.126 -1.433
-0.679 -0.807 -0.918 -0.863 -0.760
-1.039 -1.108 -1.177 -1.126 -1.433
-0.679 -0.807 -0.918 -0.863 -0.760
-1.039 -1.108 -1.177 -1.126 -1.433
-0.679 -0.807 -0.918 -0.863 -0.760
-1.039 -1.108 -1.177 -1.126 -1.433
-0.679 -0.807 -0.918 -0.863 -0.760
1.181
0.821
1.181
0.821
1.181
0.821
1.181
0.821
V
1.1V
Stratix III Device Handbook, Volume 2
using regional clock, add the value
CCL
-2
=
V
1.269
0.968
1.269
0.968
1.269
0.968
1.269
0.968
1.1V
CCL
-3
=
V
1.352
1.093
1.352
1.093
1.352
1.093
1.352
1.093
1.1V
CCL
-4
=
V
1.293
1.030
1.293
1.030
1.293
1.030
1.293
1.030
1.1V
CCL
=
-4L
V
1.594
0.921
1.594
0.921
1.594
0.921
1.594
0.921
0.9V
CCL
1–55
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns