EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 290

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Memory Interfaces Pin Support
Figure 8–9. Memory Clock Generation Block Diagram
Note to
(1)
(2)
8–20
Stratix III Device Handbook, Volume 1
System Clock
Refer to
The mem_clk[0] and mem_clk_n[0] pins for DDR3, DDR2, and DDR SDRAM interfaces uses the I/O input
buffer for feedback. For memory interfaces using a differential DQS input, the input feedback buffer is configured
as differential input; for memory interfaces using a single-ended DQS input, the input buffer is configured as a
single-ended input. Using a single-ended input feedback buffer requires that V
V
REF
Figure
pins.
Table 8–3
8–9:
V CC
V CC
on
page 8–7
Memory Clock Pins
In addition to DQS (and CQn) signals to capture data, DDR3, DDR2, DDR
SDRAM, and RLDRAM II use an extra pair of clocks, called CK and CK#
signals, to capture the address and control/command signals. The
CK/CK# signals should be generated to mimic the write data-strobe
using Stratix III DDR I/O registers (DDIOs) to ensure that timing
relationships between CK/CK# and DQS signals (t
and DDR SDRAM or t
SRAM devices use the same clock (K/K#) to capture data, address, and
control/command signals.
The memory clock pins in Stratix III devices are generated using a DDIO
register going to differential output pins, marked in the pin table with
DIFFOUT, DIFFIO_TX, and DIFFIO_RX prefixes. For more information
on which pins to use for memory clock pins, refer to
page
Figure 8–9
Stratix III devices.
for pin location requirements for these pins.
FPGA LEs
8–7.
shows the memory clock generation block diagram for
I/O Elements
CKDK
Note
D
D
(1),
in RLDRAM II) are met. QDRII+ and QDRII
Q
Q
(2)
REF
is provided to that I/O bank’s
DQSS
Table 8–3
CK# or DK# or K#
Altera Corporation
in DDR3, DDR2,
November 2007
CK or DK or K
on