EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 385

no-image

EP3SE50F780I3N

Manufacturer Part Number
EP3SE50F780I3N
Description
Stratix III
Manufacturer
Altera
Datasheets

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SE50F780I3N
Manufacturer:
ALTERA
Quantity:
540
Part Number:
EP3SE50F780I3N
Manufacturer:
ALTERA
0
Part Number:
EP3SE50F780I3N
Manufacturer:
ALTERA
Quantity:
200
Part Number:
EP3SE50F780I3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP3SE50F780I3N
0
Figure 11–9. Multi-Device Fast AS Configuration
Note to
(1)
Altera Corporation
November 2007
Connect the pull-up resistors to a 3.3-V supply.
Figure
Serial Configuration
Device
11–9:
DATA
DCLK
ASDI
nCS
V
CC
10 kΩ
(1)
PS configuration scheme. Any other Altera device that supports PS
configuration can also be part of the chain as a configuration slave.
Figure 11–9
As shown in
devices are connected together with external pull-up resistors. These pins
are open-drain bidirectional pins on the devices. When the first device
asserts nCEO (after receiving all of its configuration data), it releases its
CONF_DONE pin. But the subsequent devices in the chain keep this shared
CONF_DONE line low until they have received their configuration data.
When all target devices in the chain have received their configuration
data and have released CONF_DONE, the pull-up resistor drives a high
level on this line and all devices simultaneously enter initialization mode.
If an error occurs at any point during configuration, the nSTATUS line is
driven low by the failing device. If you enable the Auto-restart
configuration after error option, reconfiguration of the entire chain begins
after a reset time-out period (maximum of 100 ms). If the Auto-restart
configuration after error option is turned off, the external system must
monitor nSTATUS for errors and then pulse nCONFIG low to restart
configuration. The external system can pulse nCONFIG if it is under
system control rather than tied to V
V
CC
10 kΩ
(1)
GND
V
CC
10 kΩ
(1)
shows the pin connections for this setup.
Figure
Stratix III FPGA Master
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
nCSO
ASDO
11–9, the nSTATUS and CONF_DONE pins on all target
MSEL2
MSEL1
MSEL0
nCEO
V
CCPGM
GND
CC
Stratix III Device Handbook, Volume 1
.
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
Stratix III FPGA Slave
Configuring Stratix III Devices
MSEL2
MSEL1
MSEL0
nCEO
GND
V
N.C.
CCPGM
11–25

Related parts for EP3SE50F780I3N