EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 448

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

IEEE Std. 1149.1 BST Operation Control
Figure 13–5. IEEE Std. 1149.1 TAP Controller State Machine
13–10
Stratix III Device Handbook, Volume 1
TMS = 1
TMS = 0
TEST_LOGIC/
RUN_TEST/
RESET
IDLE
The IEEE Std. 1149.1 TAP controller, a 16-state machine clocked on the
rising edge of TCK, uses the TMS pin to control IEEE Std. 1149.1 operation
in the device.
When the TAP controller is in the TEST_LOGIC/RESET state, the BST
circuitry is disabled, the device is in normal operation, and the instruction
register is initialized with IDCODE as the initial instruction. At device
power-up, the TAP controller starts in this TEST_LOGIC/RESET state. In
addition, forcing the TAP controller to the TEST_LOGIC/RESET state is
TMS = 0
TMS = 1
TMS = 1
TMS = 1
TMS = 0
Figure 13–5
TMS = 0
TMS = 0
TMS = 0
TMS = 1
TMS = 1
TMS = 1
CAPTURE_DR
UPDATE_DR
PAUSE_DR
SHIFT_DR
EXIT1_DR
EXIT2_DR
TMS = 0
SELECT_DR_SCAN
TMS = 0
TMS = 0
TMS = 1
TMS = 1
shows the TAP controller state machine.
TMS = 1
TMS = 1
TMS = 0
TMS = 1
TMS = 0
TMS = 0
TMS = 1
TMS = 0
TMS = 1
TMS = 1
CAPTURE_IR
UPDATE_IR
PAUSE_IR
EXIT2_IR
SHIFT_IR
EXIT1_IR
SELECT_IR_SCAN
TMS = 0
TMS = 0
TMS = 0
TMS = 1
Altera Corporation
November 2007