EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 272

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Introduction
8–2
Stratix III Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
DDR3 SDRAM
DDR2 SDRAM
DDR SDRAM
QDRII+ SRAM
QDRII SRAM
RLDRAM II
Table 8–1. Stratix III Maximum Clock Rate Support for External Memory Interfaces with Half-Rate
Controller
Memory Standards
Numbers are preliminary until characterization is final.
Performance is based on 0.9-V core voltage. At 1.1-V core voltage, the -4L speed grade devices have the same
performance as the -4 speed grade devices.
Left/right I/O banks have lower maximum performance than the top/bottom I/O banks due to the left/right
I/Os having higher pin capacitance to support the LVDS I/O standard.
This applies for interfaces with both modules and components.
Memory interfaces above 333 MHz require the use of the deskew circuitry pending characterization.
Support will be evaluated after characterization.
Stratix III FPGAs support QDRII+ SRAM devices with 2.5 cycle read latency. Stratix III FPGAs do not support
QDRII+ SRAM devices with 2.0 cycle read latency.
This applies to QDRII SRAM and RLDRAM II devices running at 1.5-V and 1.8-V I/O voltages.
Table
Note (1)
(8)
(8)
(4)
8–1:
(7)
(4)
(4)
I/O Banks
Bottom
400
400
350
350
400
–2 Speed Grade
Top/
200
(5)
(5)
(5)
(5)
(5)
Table 8–1
devices can support with external memory devices.
(MHz)
Banks
Right
Left/
300
300
200
300
300
300
I/O
(3)
and
Table 8–2
I/O Banks
Bottom
–3 Speed Grade
Top/
333
333
200
300
300
300
(MHz)
summarize the maximum clock rate Stratix III
TBD
Banks
Right
Left/
267
200
250
250
250
I/O
(3)
(6)
Bottom
Banks
–4 Speed Grade
Top/
333
333
200
300
300
300
I/O
(MHz)
TBD
Banks
Right
Left/
267
200
250
250
250
I/O
(3)
(6)
Altera Corporation
-4L Speed Grade
Bottom
Banks
Top/
200
200
167
November 2007
I/O
—
—
—
(MHz)
(2)
Banks
Right
Left/
167
167
133
I/O
—
—
—