EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 419

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
TDI
TDO
TMS
Pin Name User Mode Pin Type
Table 11–16. Dedicated JTAG Pins (Part 1 of 2)
N/A
N/A
N/A
Input
Output
Input
25 kΩ). If you plan to use the SignalTap
you need to connect the JTAG pins of the Stratix III device to a JTAG
header on your board.
Serial input pin for instructions as well as test and programming data. Data
is shifted in on the rising edge of
2.5-V/3.0-V/3.3-V V
If the JTAG interface is not required on the board, you can disable the JTAG
circuitry by connecting this pin to V
Serial data output pin for instructions as well as test and programming data.
Data is shifted out on the falling edge of
not being shifted out of the device. The
recommendations on connecting a JTAG chain with multiple voltages
across the devices in the chain, refer to the chapter IEEE 1149.1 (JTAG)
Boundary Scan Testing in Stratix III Devices chapter in volume 1 of the
Stratix III Device Handbook.
If the JTAG interface is not required on the board, you can disable the JTAG
circuitry by leaving this pin unconnected.
Input pin that provides the control signal to determine the transitions of the
TAP controller state machine. Transitions within the state machine occur on
the rising edge of
edge of
powered by the 2.5-V/3.0-V/3.3-V V
If the JTAG interface is not required on the board, you can disable the JTAG
circuitry by connecting this pin to V
TCK
.
TMS
TCK
is evaluated on the rising edge of
CCPD
. Therefore,
supply.
Description
TCK
TMS
CC
CC
Stratix III Device Handbook, Volume 1
CCPD
.
.
. The
®
TDO
must be set up before the rising
embedded logic array analyzer,
.
TCK
TDI
Configuring Stratix III Devices
. The pin is tri-stated if data is
pin is powered by V
pin is powered by the
TCK
. The
TMS
CCPD
pin is
11–59
For