EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 266

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Design Considerations
7–48
Stratix III Device Handbook, Volume 1
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards
An I/O bank can support both non-voltage-referenced and
voltage-referenced pins by applying each of the rule sets individually.
For example, an I/O bank can support SSTL-18 inputs and 1.8-V inputs
and outputs with a 1.8-V V
can support 1.5-V standards, 1.8-V inputs (but not outputs), and HSTL
and HSTL-15 I/O standards with a 1.5-V V
I/O Placement Guidelines
This section provides I/O placement guidelines for the programmable
I/O standards supported by Stratix III devices and includes essential
information for designing systems using a Stratix III device’s selectable
I/O capabilities.
I/O Pin Placement with Respect to LVDS I/O Pins
The placement of single-ended I/O pins with respect to LVDS I/O pins is
restricted. As shown in
single-ended outputs with driving strength equal to or greater than 8 mA
at least one row away from the LVDS I/O. The same restriction applies to
single-ended inputs with OCT R
with driving strength less than 8 mA in the rows adjacent to the LVDS
I/O. The restriction does not apply when you use the LVDS input buffer
for differential HSTL/SSTL input. Single-ended inputs without OCT R
have no placement restriction. When DPA is enabled, the constraint on
single-ended I/O is the same as that on regular LVDS I/O.
Figure
CCIO
7–30, you should place row I/O
and a 0.9-V V
T
. You can place single-ended outputs
CCIO
REF
and 0.75-V V
. Similarly, an I/O bank
Altera Corporation
November 2007
REF
.
T