EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 286

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Memory Interfaces Pin Support
8–16
Stratix III Device Handbook, Volume 1
The DQS and DQSn pins are listed in the Stratix III pin tables as
DQSXY and DQSnXY, respectively, where X denotes the DQS/DQ
grouping number, and Y denotes whether the group is located on the top
(T), bottom (B), left (L), or right (R) side of the device.
The corresponding DQ pins are marked as DQXY, where X indicates
which DQS group the pins belong to and Y indicates whether the group
is located on the top (T), bottom (B), left (L), or right (R) side of the device.
For example, DQS1L indicates a DQS pin, located on the left side of the
device. See
group will be shown as DQ1L in the pin table.
The numbering scheme starts from the top left side of the device going
counter-clockwise.
numbered in a package-bottom view of the device. The top and bottom
sides of the device can contain up to 44 ×4 DQS/DQ groups, and the left
and right sides of the device can contain up to 40 ×4 DQS/DQ groups.
The parity, DM, BWSn, ECC, and QVLD pins are shown as DQ pins in the
pin table. When not used as memory interface pins, these pins are
available as regular I/O pins.
Figure 8–8
Figure 8–8
for illustrations. The DQ pins belonging to that
shows how the DQS/DQ groups are
Altera Corporation
November 2007