EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 163
EP3SE50F780I3N
Manufacturer Part Number
EP3SE50F780I3N
Description
Stratix III
Manufacturer
Altera
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Quantity
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Part Number:
EP3SE50F780I3N
Manufacturer:
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Altera Corporation
November 2007
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
CLK12
CLK13
CLK14
CLK15
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
Table 6–7. Stratix III Device PLLs and PLL Clock Pin Drivers (Part 2 of 2)
Table 6–8. Stratix III PLL Connectivity to GCLKs (Part 1 of 2)
Dedicated Clock
(CLKp/n pins)
Clock Network
Input Pin
L1
—
—
—
—
—
—
—
—
—
—
—
—
v
L1
v
v
v
—
—
—
v
Clock Output Connections
PLLs in Stratix III devices can drive up to 20 regional clock networks and
4 global clock networks. Refer to
to GCLK networks. The Quartus II software automatically assigns PLL
clock outputs to regional or global clock networks.
Table 6–8
L2
—
—
—
—
—
—
—
—
—
—
—
—
v
L2
v
v
—
—
—
v
v
L3
—
—
—
—
—
—
—
—
—
—
—
—
v
L3
v
v
v
—
—
—
v
shows how the PLL clock outputs connect to GCLK networks.
L4
—
—
—
—
—
—
—
—
—
—
—
—
v
L4
v
v
v
—
—
—
v
B1
v
v
v
v
—
—
—
—
—
—
—
—
—
B1
v
v
v
—
—
—
—
B2
—
v
v
—
—
—
—
—
—
—
—
PLL Number
PLL Number
v
v
B2
v
v
v
—
—
—
—
Clock Networks and PLLs in Stratix III Devices
Table 6–8
R1
—
—
—
—
—
—
—
—
—
v
v
v
v
R1
—
—
—
—
—
—
—
Stratix III Device Handbook, Volume 1
R2
—
—
—
—
—
—
—
—
—
v
v
v
v
R2
—
—
—
—
—
—
—
for Stratix III PLL connectivity
R3
—
—
—
—
—
—
—
—
—
R3
v
v
v
v
—
—
—
—
—
—
—
R4
—
—
—
—
—
—
—
R4
—
—
—
—
—
—
—
—
—
v
v
v
v
T1
—
—
—
—
—
—
—
T1
—
—
—
—
—
—
—
—
—
v
v
v
v
T2
—
—
—
—
—
—
—
T2
—
—
—
—
—
—
—
—
—
v
v
v
v
6–13
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