EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 321

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 9–2. Stratix III Transmitter Block Diagram
Altera Corporation
November 2007
Internal
Logic
Any Stratix III transmitter data channel can be configured to generate a
source synchronous transmitter clock output. This flexibility allows
placing the output clock near the data outputs to simplify board layout
and reduce clock-to-data skew. Different applications often require
specific clock-to-data alignments or specific data rate to clock rate factors.
The transmitter can output a clock signal at the same rate as the data with
a maximum frequency of 717 MHz. The output clock can also be divided
by a factor of 2, 4, 8, or 10, depending on the serialization factor. The
phase of the clock in relation to the data can be set at 0° or 180° (edge or
center aligned). The left and right PLLs (PLL_Lx/PLL_Rx) provide
additional support for other phase shifts in 45° increments. These settings
are made statically in the Quartus II MegaWizard
shows the Stratix III transmitter in clock output mode.
PLL_Lx /
PLL_Rx
10
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
load_en
diffioclk
Serializer
Stratix III Device Handbook, Volume 1
TX_OUT
®
software.
Figure 9–3
9–5