EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 168

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Clock Networks in Stratix III Devices
6–18
Stratix III Device Handbook, Volume 1
Figure 6–12. Regional Clock Control Block
Note to
(1)
The clock source selection for the regional clock select block can only be
controlled statically using configuration bit settings in the configuration
file (.sof or .pof) generated by the Quartus II software.
The Stratix III clock networks can be powered down by both static and
dynamic approaches. When a clock net is powered down, all the logic fed
by the clock net is in an off-state, thereby reducing the overall power
consumption of the device. The unused global and regional clock
networks are automatically powered down through configuration bit
settings in the configuration file (.sof or .pof) generated by the Quartus II
software. The dynamic clock enable or disable feature allows the internal
logic to control power-up or power-down synchronously on GCLK and
RCLK networks, including dual-regional clock regions. This function is
independent of the PLL and is applied directly on the clock network, as
shown in
You can set the input clock sources and the clkena signals for the global
and regional clock network multiplexers through the Quartus II software
using the altclkctrl megafunction. You can also enable or disable the
dedicated external clock output pins using the altclkctrl megafunction.
Figure 6–13
This clock select signal can only be dynamically controlled through a configuration
file (.SOF or .POF) and cannot be dynamically controlled during user mode
operation.
Figure
PLL Counter
Figures 6–11
shows the external PLL output clock control block.
Outputs
6–12:
and 6–12.
2
CLKp
Pin
Enable/
Disable
RCLK
CLKn
Pin
Internal
Logic
Static Clock Select (1)
Internal
Logic
Altera Corporation
November 2007