EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 355

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Hot Socketing
Feature
Implementation
in Stratix III
Devices
Figure 10–1. Hot Socketing Circuit Block Diagram for Stratix III Devices
Altera Corporation
October 2007
Resistor
Pull-Up
Weak
PAD
within the device. As a result, the device draws a large amount of current,
possibly causing electrical damage. Nevertheless, Stratix III devices are
immune to latch-up when hot-socketing.
The hot socketing feature turns off the output buffer during power-up
and power-down of V
hot socketing circuitry generates an internal HOTSCKT signal when the
V
voltage. The hot socketing circuitry is designed to prevent excess I/O
leakage during power-up. When the voltage ramps up very slowly, it is
still relatively low, even after the POR signal is released and the
configuration is completed. The CONF_DONE, nCEO, and nSTATUS pins
fail to respond, as the output buffer cannot flip from the state set by the
hot socketing circuit at this low voltage. Therefore, the hot socketing
circuit has been removed on these configuration pins to make sure that
they are able to operate during configuration. Thus, it is expected
behavior for these pins to drive out during power-up and power-down
sequences.
Each I/O pin has the following circuitry shown in
R
CC
, V
CCIO
V
CCIO
, V
CCPGM
Hot Socketing and Power-On Reset in Stratix III Devices
, or V
CC
Tolerance
, V
to Logic Array
CCPD
Voltage
Control
Input Buffer
CCIO
power supplies are below the threshold
, V
Output Enable
CCPGM
Stratix III Device Handbook, Volume 1
, or V
Pre-Driver
Hot Socket
Output
CCPD
Power On
Monitor
Reset
power supplies. The
Figure
10–1.
10–3