EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 80

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Overview
Figure 4–3. Stratix III Address Clock Enable during Read Cycle Waveform
4–6
Stratix III Device Handbook, Volume 1
latched address
(inside memory)
addressstall
q (asynch)
rdaddress
q (synch)
inclock
rden
doutn-1
doutn
an
Figure 4–2
clock enable is referred to by the port name addressstall.
Figure 4–2. Stratix III Address Clock Enable Block Diagram
Figure 4–3
cycle.
a0
doutn
a0
dout0
addressstall
address[0]
address[N]
a1
shows an address clock enable block diagram. The address
shows the address clock enable waveform during the read
clock
dout0
a2
a1
dout1
1
0
1
0
a3
dout1
address[0]
address[N]
register
register
a4
a4
dout4
a5
address[0]
address[N]
Altera Corporation
dout4
a5
dout5
November 2007
a6