EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 111

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II GX Devices
PLLs in Arria II GX Devices
© July 2010
Altera Corporation
Figure 5–13. Source-Synchronous Mode for LVDS Compensation
No-Compensation Mode
In no-compensation mode, the PLL does not compensate for the clock networks. This
mode provides better jitter performance because the clock feedback into the phase
frequency detector (PFD) passes through less circuitry. Both the PLL internal- and
external-clock outputs are phase-shifted with respect to the PLL clock input.
Figure 5–14
no-compensation mode.
Figure 5–14. Phase Relationship Between PLL Clocks in No Compensation Mode
Note to
(1) The PLL clock outputs can lag the PLL input clocks depending on routine delays.
Figure
External PLL Clock Outputs (1)
5–14:
shows an example waveform of the PLL clocks’ phase relationship in
Register Clock Port (1)
Clock at register
reference clock
Data at register
PLL Clock at the
PLL Reference
at input pin
Clock at the
Data pin
Input Pin
PLL
Phase Aligned
Arria II GX Device Handbook, Volume 1
5–19