EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 91
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 4: DSP Blocks in Arria II GX Devices
Operational Mode Descriptions
Table 4–9. DSP Block Dynamic Signals for DSP Block (Part 2 of 2)
© July 2010
chainout_saturate
accum_sload
zero_chainout
zero_loopback
rotate
shift_right
DSP Block Dynamic Signals per Full-DSP Block
clock0
clock1
clock2
clock3
ena0
ena1
ena2
ena3
aclr0
aclr1
aclr2
aclr3
Signal Name
Altera Corporation
—
Saturation control for second stage round/saturation block for
Q-format multiply. If both rounding and saturation is enabled,
saturation is done on the rounded result.
■
■
Dynamically specifies whether the accumulator value is zero.
■
■
Dynamically specifies whether the chainout value is zero.
Dynamically specifies whether the loopback value is zero.
rotation = 1, rotation feature is enabled
shift_right = 1, shift right feature is enabled
DSP-block-wide clock signals
Input and Pipeline Register enable signals
DSP block-wide asynchronous clear signals (active low)
Total Count per Half- and Full-DSP Blocks
chainout_saturate = 1 for saturation support
chainout_saturate = 0 for no saturation support
accum_sload = 0, accumulation input is from the output
registers
accum_sload = 1, accumulation input is set to be zero
Function
Arria II GX Device Handbook, Volume 1
Count
33
1
1
1
1
1
1
4
4
4
4–31
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