EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 183

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II GX Devices
Arria II GX External Memory Interface Features
Figure 7–17. Arria II GX IOE Output and Output Enable Path Registers
Notes to
(1) You can bypass each register block of the output and output-enable paths.
(2) The write clock comes from the PLL. The DQ write clock and DQS write clock have a 90° offset between them.
© July 2010 Altera Corporation
Figure
7–17:
Figure 7–17
paths. The device can bypass each block of the output and output enable path.
The output path is designed to route combinatorial or registered single data rate
(SDR) outputs and DDR outputs from the FPGA core.
The output enable path has a structure similar to the output path. You can have a
combinatorial or registered output in SDR applications.
datahi
From core
datainlo
From core
Write
Clock (2)
OE
From core
shows the registers available in the Arria II GX output and output enable
DFF
DFF
Output Reg Bo
Double Data Rate Output-Enable Registers
Output Reg Ao
OE Reg B
OE Reg A
DFF
DFF
D
D
D
D
Double Data Rate Output Registers
Q
Q
Q
Q
OE
OE
1
0
dataout
OR2
(Note 1)
dataout
TRI
Arria II GX Device Handbook, Volume 1
DQ or DQS
7–25