EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 290

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

10–6
Error Detection Registers
Figure 10–1. Error Detection Circuitry, Syndrome Registers, and Error Injection Block
Table 10–5. Error Detection Registers (Part 1 of 2)
Arria II GX Device Handbook, Volume 1
Syndrome Register
Error Message
Register
Readback
bitstream with
expected CRC
included
Register
Error Injection Block
Injection Register
Fault Injection
JTAG Fault
Register
There is one set of 16-bit registers in the error detection circuitry that stores the
computed CRC signature. A non-zero value on the syndrome register causes the
CRC_ERROR pin to be set high.
Figure 10–1
registers, and error injection block.
Table 10–5
Error Detection
State Machine
This register contains the CRC signature of the current frame through the error detection
verification cycle. The CRC_ERROR signal is derived from the contents of this register.
This 46-bit register contains information on the error type, location of the error, and the actual
syndrome. The types of errors and location reported are single- and double-adjacent bit errors.
The location bits for other types of errors are not identified by the error message register. The
content of the register is shifted out through the JTAG SHIFT_EDERROR_REG instruction or to
the core through the core interface.
lists the registers shown in
shows the block diagram of the error detection circuitry, syndrome
Control Signals
JTAG Update
JTAG TDO
JTAG Shift
Register
Register
Calculation and Error
Error Message
Search Engine
16-Bit CRC
Figure
Register
Description
30
46
10–1.
General Routing
User Update
User Shift
Register
Chapter 10: SEU Mitigation in Arria II GX Devices
Register
8
© July 2010 Altera Corporation
Syndrome
Register
16
Error Detection Block
CRC_ERROR