EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 42

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–2
Memory Block Types
Parity Bit Support
Arria II GX Device Handbook, Volume 1
Table 3–1. Summary of Memory Features (Part 2 of 2)
Table 3–2
family member.
Table 3–2. Memory Capacity and Distribution in Arria II GX Devices
M9K memory blocks are dedicated resources; MLABs are dual-purpose blocks. You
can configure the MLABs as regular logic array blocks (LABs) or as MLABs. Ten
ALMs make up one MLAB. You can configure each ALM in an MLAB as either a
64 × 1 or a 32 × 2 block, resulting in a 64 × 10 or 32 × 20 simple dual-port SRAM block
in a single MLAB.
All memory blocks have built-in parity bit support. The ninth bit associated with each
byte can store a parity bit or serve as an additional data bit. No parity function is
actually performed on the ninth bit.
FIFO buffer
Simple dual-port mixed width support
True dual-port mixed width support
Memory initialization file (.mif)
Mixed-clock mode
Power-up condition
Register clears
Write/Read operation triggering
Same-port read-during-write
Mixed-port read-during-write
ECC Support
Note to
(1) These numbers are preliminary.
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
Device
Table
lists the capacity and distribution of the memory blocks in each Arria II GX
3–1:
Feature
MLABs
1,265
1,874
2,482
3,806
5,130
903
M9K Blocks
319
495
612
730
840
950
Outputs cleared if
registered, otherwise
reads memory contents.
Output registers
Write: Falling clock edges
Read: Rising clock edges
Outputs set to old data
Outputs set to old data or
don’t care
Soft IP support using
Quartus II software
MLABs
v
v
v
—
—
Total RAM Bits (including MLABs) (Kbits)
Chapter 3: Memory Blocks in Arria II GX Devices
© November 2009 Altera Corporation
Outputs cleared
Output registers
Write and Read: Rising
clock edges
Outputs set to old data
or new data
Outputs set to old data
or don’t care
Soft IP support using
Quartus II software
11,756
3,435
5,246
6,679
8,121
9,939
M9K Blocks
v
v
v
v
v
Memory Features