EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 120

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–28
Figure 5–21. Clock Switchover with the clkswitch (Manual) Control
Note to
(1) To start a manual clock switchover event, both inclk0 and inclk1 must be running when the clkswitch signal goes high.
Arria II GX Device Handbook, Volume 1
Figure
5–21:
In automatic switchover with manual overide mode, the activeclock signal
mirrors the clkswitch signal. As both clocks are still functional during the manual
switch, neither clkbad signal goes high. Because the switchover circuit is
positive-edge sensitive, the falling edge of the clkswitch signal does not cause the
circuit to switch back from inclk1 to inclk0. When the clkswitch signal goes
high again, the process repeats. The clkswitch signal and automatic switch only
work if the clock being switched to is available. If the clock is not available, the state
machine waits until the clock is available.
Manual Clock Switchover Mode
In manual clock switchover mode, the clkswitch signal controls whether inclk0
or inclk1 is selected as the input clock to the PLL. By default, inclk0 is selected. A
low-to-high transition on clkswitch and clkswitch being held high for at least
three inclk cycles begins a clock switchover event. You must bring the clkswitch
signal back low again to perform another switchover event in the future. If you do not
require another switchover event in the future, you can leave clkswitch in a logic
high state after the initial switch. Pulsing clkswitch high for at least three inclk
cycles performs another switchover event. If inclk0 and inclk1 are different
frequencies and are always running, the clkswitch minimum high time must be
greater than or equal to three of the slower frequency inclk0 and inclk1 cycles.
activeclock
clkswitch
clkbad0
clkbad1
muxout
inclk0
inclk1
(Note 1)
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
© July 2010 Altera Corporation
PLLs in Arria II GX Devices