EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 225

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Configuration Process
Reset
Configuration
Configuration Error
© July 2010
Altera Corporation
After power up, the Arria II GX device goes through a POR. The POR delay depends
on the MSEL pin settings. During POR, the device resets, holds nSTATUS low, clears
the configuration RAM bits, and tri-states all user I/O pins. After the device
successfully exits POR, all user I/O pins continue to be tri-stated. While nCONFIG is
low, the device is in reset. When the device comes out of reset, nCONFIG must be at a
logic-high level in order for the device to release the open-drain nSTATUS pin. After
nSTATUS is released, it is pulled high by a pull-up resistor and the device is ready to
receive configuration data.
Before and during configuration, all user I/O pins are tri-stated. If nIO_pullup is
driven low during power up and configuration, the user I/O pins and dual-purpose
I/O pins have weak pull-up resistors, which are on (after POR) before and during
configuration. If nIO_pullup is driven high, the weak pull-up resistors are disabled.
nCONFIG and nSTATUS must be at a logic-high level in order for the configuration
stage to begin. The device receives configuration data on its DATA pins and (for
synchronous configuration schemes) the clock source on the DCLK pin. Configuration
data is latched into the FPGA on the rising edge of DCLK. After the FPGA has received
all the configuration data successfully, it releases the CONF_DONE pin, which is pulled
high by a pull-up resistor. A low-to-high transition on CONF_DONE indicates
configuration is complete and initialization of the device can begin.
To ensure DCLK and DATA0 are not left floating at the end of configuration, they must
be driven either high or low, whichever is convenient on your board. Use the
dedicated pin DATA[0] for both passive and active configuration modes. It is not
available as a user I/O pin after configuration.
For FPP and PS configuration schemes, the configuration clock (DCLK) speed must be
below the specified frequency to ensure correct configuration. No maximum DCLK
period exists, which means you can pause the configuration by halting DCLK for an
indefinite amount of time.
A reconfiguration is initiated by toggling the nCONFIG pin from high to low and then
back to high with a minimum t
configuration error, initialization, or user mode stage. When nCONFIG is pulled low,
nSTATUS and CONF_DONE are also pulled low and all I/O pins are tri-stated. After
nCONFIG and nSTATUS return to a logic-high level, configuration begins.
If an error occurs during configuration, Arria II GX devices assert the nSTATUS signal
low, indicating a data frame error; the CONF_DONE signal stays low. If the Auto-restart
configuration after error option (available in the Quartus II software from the
General tab of the Device and Pin Options dialog box) is turned on, the Arria II GX
device resets the configuration device and retries the configuration. If this option is
turned off, the system must monitor nSTATUS for errors and then pulse nCONFIG low
to restart the configuration.
CFG
low-pulse width either in the configuration,
Arria II GX Device Handbook, Volume 1
9–5