EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 283

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Document Revision History
Document Revision History
Table 9–23. Document Revision History
© July 2010
July 2010
November 2009
June 2009
February 2009
Date
Altera Corporation
Version
Table 9–23
3.0
2.0
1.1
1.0
Updated for Arria II GX v10.0 release:
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Updated for Arria II GX v9.1 release:
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Initial release.
shows the revision history for this chapter.
Updated
Updated
and
Updated
Security Key Storage”
Added
on Active Serial Interface”
Minor text edits.
Updated Table 9–3, Table 9–10, Table 9–11, Table 9–13.
Updated Figure 9–2, Figure 9–3, and Figure 9–6.
Updated “VCCPD Pins”, “JTAG Configuration”, “Remote System Upgrade Mode”,
“Remote System Upgrade State Machine”, “User Watchdog Timer” sections.
Minor text edits.
Updated Table 9–2, Table 9–3, Table 9–9, Table 9–10, Table 9–19, and Table 9–21.
Updated Figure 9–6, Figure 9–11, and Figure 9–16.
Updated “VCCIO Pins for I/O Banks 3C and 8C”, “FPP Configuration Using an
External Host”, and “Programming Serial Configuration Devices” sections.
Removed “Volatite or Non-Volatile Key with JTAG Anti-Tamper Protection Bit Set”
section.
Figure
“Guidelines for Connecting Serial Configuration Device to Arria II GX Devices
Table 9–3
Figure
“Active Serial Configuration (Serial Configuration Devices)”
9–30.
9–4,
and
Figure
sections.
Table
section.
9–5,
9–11.
Figure
Changes Made
9–13,
Figure
9–16,
Arria II GX Device Handbook, Volume 1
Figure
9–17,
and
Figure
“Flexible
9–21,
9–63