EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 141

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Arria II GX Devices
Arria II GX I/O Structure
External Memory Interfaces
High-Speed Differential I/O with DPA Support
© July 2010 Altera Corporation
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When you use the Arria II GX device as a transmitter, techniques to limit overshoot
and undershoot at the I/O pins include using slow slew rate and series termination.
Transmission line effects that cause large voltage deviations at the receiver are
associated with an impedance mismatch between the driver and transmission line. By
matching the impedance of the driver to the characteristic impedance of the
transmission line, you can significantly reduce overshoot voltage. You can use a series
termination resistor placed physically close to the driver to match the total driver
impedance to transmission line impedance. Other than 3.3-V LVTTL and 3.3-V
LVCMOS I/O standards, Arria II GX devices support R
I/O standards in all I/O banks.
When you use the Arria II GX device as a receiver, use a clamping diode (on-chip or
off-chip) to limit overshoot, though limiting overshoot is not required. Arria II GX
devices provide an optional on-chip PCI clamp diode for I/O pins. You can use this
diode to protect I/O pins against overshoot voltage.
Another method for limiting overshoot is reducing the bank supply voltage (V
3.0 V. In this method, the clamp diode (on-chip or off-chip), though not required, can
sufficiently clamp overshoot voltage to in the DC- and AC-input voltage specification.
The clamped voltage can be expressed as the sum of the supply voltage (V
diode forward voltage. By lowering V
undershoot for all I/O standards, including 3.3-V LVTTL/LVCMOS, 3.0-V
LVTTL/LVCMOS, and 3.0-V PCI/PCI-X. Additionally, lowering V
power consumption.
For more information about absolute maximum rating and maximum allowed
overshoot during transitions, refer to the
In addition to I/O registers in each IOE, Arria II GX devices also have dedicated
registers and phase-shift circuitry on all I/O banks for interfacing with external
memory interfaces.
For more information about external memory interfaces, refer to the
Interfaces in Arria II GX Devices
Arria II GX devices have the following dedicated circuitry for high-speed differential
I/O support:
■
■
■
■
■
■
■
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment circuitry
Dynamic phase aligner (DPA)
Synchronizer (FIFO buffer)
Phase-locked loops (PLLs)
chapter.
CCIO
Arria II GX Devices
to 3.0 V, you can reduce overshoot and
S
OCT for all LVTTL/LVCMOS
Arria II GX Device Handbook, Volume 1
Datasheet.
CCIO
External Memory
to 3.0 V reduces
CCIO
) and the
CCIO
) to
6–7