EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 22

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–8
DSP Resources
I/O Features
Arria II GX Device Handbook, Volume 1
Table 1–5
Table 1–5. Memory Modes for Arria II GX Devices
■
■
■
■
■
■
Table 1–6. I/O Standards Support for Arria II GX Devices
■
■
■
■
Single Port
Simple Dual Port
True Dual Port
Single-Ended I/O
Differential I/O
Fulfills the DSP requirements of 3G and Long Term Evolution (LTE) wireless
infrastructure applications, video processing applications, and voice processing
applications
DSP block input registers efficiently implement shift registers for finite impulse
response (FIR) filter applications
The Quartus II software includes megafunctions you can use to control the mode
of operation of the DSP blocks based on user-parameter settings
You can directly infer multipliers from the VHDL or Verilog HDL source code
Contains up to 12 modular I/O banks
All I/O banks support a wide range of single-ended and differential I/O
standards, as listed in
Supports programmable bus hold, programmable weak pull-up resistors, and
programmable slew rate control
Calibrates OCT or driver impedance matching for single-ended I/O standards
with one OCT calibration block on the top-left, top-right, and bottom-left corners
of the device
Dedicated configuration banks at Bank 3C and 8C which support dedicated
configuration pins and some of the dual-purpose pins with a configuration
scheme at 1.8, 2.5, 3.0, and 3.3 V
Dedicated VREF pin per I/O bank to allow voltage-referenced I/O standards. Each
I/O bank can operate at independent V
Port Mode
Type
lists the Arria II GX device memory modes.
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
×1, ×2, ×4, ×8, ×9, ×16, and ×18
LVTTL, LVCMOS, SSTL, HSTL, PCIe, and PCI-X
SSTL, HSTL, LVPECL, LVDS, mini-LVDS, Bus LVDS (BLVDS), and RSDS
Table 1–6
Port Width Configuration
CCIO
and V
I/O Standard
Chapter 1: Arria II GX Device Family Overview
REF
levels
© July 2010 Altera Corporation
Arria II GX Device Architecture