EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 188

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–4
Table 8–1. LVDS Channels Supported in Arria II GX Device Row I/O Banks
Arria II GX Device Handbook, Volume 1
Notes to
(1) Dedicated SERDES and DPA circuitry only exist on the right side of the device in the Row I/O banks.
(2) RD = True LVDS input buffers with R
(3) RX = True LVDS input buffers without R
(4) TX = True LVDS output buffers and dedicated SERDES transmitter channel.
(5) eTX = Emulated LVDS output buffers, either LVDS_E_3R or LVDS_E_1R.
(6) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins.
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGX45
EP2AGX65
EP2AGX95
Device
Table
8–1:
1
358-Pin FlipChip UBGA
8(RX, TX, or eTX)
8(RX, Tx or eTx)
8(RD or eTX) +
8(RD or eTX) +
Table 8–1
supported in Arria II GX devices. You can design the LVDS I/Os as true LVDS input,
output buffers, or emulated LVDS output buffers, as long as the combination does not
exceed the maximum count. For example, there are a total of 56 LVDS pairs of I/Os in
780-pin EP2AGX45 device row (refer to
of either:
■
■
■
■
SERDES with DPA receivers are only available on RD pins and SERDES transmitters
are only available on TX pins.
—
—
—
—
28 true LVDS input buffers with R
56 LVDS input buffers of which 28 are true LVDS input buffers with R
28 requires external 100-termination
28 true LVDS output buffers and 28 emulated LVDS output buffers
56 emulated LVDS output buffers
and
D
OCT support and dedicated SERDES receiver channel with DPA.
D
OCT support.
Table 8–2
572-Pin FlipChip FBGA
24(RX, TX, or eTX)
24(Rx, TX, or eTX)
24(RX, TX or eTX)
24(RX, TX or eTX)
24(RD or eTX) +
24(RD or eTX) +
24(RD or eTX) +
24(RD or eTx) +
list the maximum number of row and column LVDS I/Os
—
—
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
D
OCT and 28 true LVDS output buffers
Table
780-Pin FlipChip FBGA
28(RX, TX, or eTX)
28((RX, TX or eTX)
28(RX, TX or eTX)
28(RX, TX or eTX)
28(RX, TX or eTX)
28(RX, TX or eTX)
(Note
28(RD or eTX) +
28(RD or eTX) +
28(RD or eTX) +
28(RD or eTX) +
28(RD or eTX) +
28(RD or eTX)+
8–1). You can design up to a maximum
1), (2), (3), (4), (5),
© July 2010 Altera Corporation
1152-Pin FlipChip FBGA
(6)
32(RX, TX, or eTX)
32(RX, TX or eTX)
48(RX, TX or eTX)
48(RX, TX or eTX)
32(RD or eTX) +
32(RD or eTX) +
48(RD or eTX) +
48(RD or eTX) +
D
LVDS Channels
OCT and
—
—