EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 211

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EP2AGX95EF29I5N

Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX95EF29I5N

Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP2AGX95EF29I5N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2AGX95EF29I5N
Manufacturer:
ALTERA
0
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Differential Pin Placement Guidelines
© July 2010
Altera Corporation
Using Both Corner PLLs
You can use both corner PLLs to drive DPA-enabled channels simultaneously, as long
as they drive the channels in their adjacent banks only. There must be at least one row
of separation between the two groups of DPA-enabled channels.
If one of the corner PLLs drives DPA-enabled channels in the upper and lower I/O
banks, you cannot use the center PLLs. You can use the other corner PLL to drive
DPA-enabled channels in their adjacent bank only. There must be at least one row of
separation between the two groups of DPA-enabled channels.
If the upper corner PLL drives DPA-enabled channels in the lower I/O bank, the
lower corner PLL cannot drive DPA-enabled channels in the upper I/O bank, and vice
versa. In other words, the corner PLLs cannot drive cross-banks simultaneously, as
shown in
Figure
8–24.
Arria II GX Device Handbook, Volume 1
8–27

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