EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 197
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Differential Receiver
Figure 8–10. Arria II GX Deserializer Bypass
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, rx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width from the IOE is 1 and 2, respectively.
Receiver Datapath Modes
© July 2010
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
Altera Corporation
8–10:
2
Arria II GX devices support three receiver datapath modes:
■
■
■
Non-DPA Mode
Non-DPA mode allows you to statically select the optimal phase between the
source-synchronous reference clock and the input serial data to compensate for any
skew between the two signals. The reference clock must be a differential signal.
Figure 8–11
registered at the rising or falling edge of the LVDS_diffioclk clock produced by the
center/corner PLL. You can select the rising/falling edge option using the ALTLVDS
megafunction. Both data realignment and deserializer blocks are clocked by the
LVDS_diffioclk clock.
When interfacing with non-DPA receivers at data rate above 840 Mbps, you must
perform PCB trace compensation to adjust the trace length of each LVDS channel to
improve the channel-to-channel skews.
IOE Supports SDR, DDR, or Non-Registered Datapath
Non-DPA mode
DPA mode
Soft CDR mode
(LOAD_EN, diffioclk)
2
Deserializer
Deser
Deserializ
DOUT DIN
shows the non-DPA datapath block diagram. Input serial data is
ializer
er
IOE
Center/Corner PLL
Center/Corner PLL
2
(Note
3
1), (2),
DOUT DIN
Multiplexer
Bit Slip
Clock
(LVDS_LO
L L
LVDS_diffioclk,
L L
p
rx_outclk)
diffioclk
(3)
AD_EN,
8 Serial LVDS
Clock Phases
Synchronizer
DOUT DIN
L L
LVDS Receiver
3
Arria II GX Device Handbook, Volume 1
(DPA_LO
DPA_diffioclk,
P P
rx_divfwdclk)
P P
AD_EN,
Retimed
DPA Circuitr
DPA Cloc
Data
P P
P P
k
DIN
y
+
rx_in
8–13
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