EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 299
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 11: JTAG Boundary-Scan Testing
I/O Voltage Support in a JTAG Chain
I/O Voltage Support in a JTAG Chain
Table 11–3. Supported TDO/TDI Voltage Combinations
© July 2010
Arria II GX
Non-Arria II GX
Notes to
(1) The TDO output buffer meets V
(2) The TDO output buffer meets V
(3) An external 250- pull-up resistor is not required; however, they are recommended if signal levels on the board are not optimal.
(4) The input buffer must be 3.0-V tolerant.
(5) The input buffer must be 2.5-V tolerant.
(6) The input buffer must be 1.8-V tolerant.
Device
Table
Altera Corporation
f
11–3:
1
TDI Input Buffer
These two instruction codes are only supported in post-configuration mode for
Arria II GX devices.
An Arria II GX device operating in BST mode uses four required pins: TDI, TDO, TMS,
and TCK. The TDO output pin and all JTAG input pins are powered by the V
supply of I/O Bank 8C.
The JTAG chain supports several devices. However, use caution if the chain contains
devices that have different V
Table 11–3
operation.
For more information about I/O voltage support in the JTAG chain, refer to the
1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices
V
V
V
V
V
V
V
V
V
C CIO
C CIO
C CIO
C CIO
C CIO
CC
CC
CC
CC
Power
= 3.3 V
= 2.5 V
= 1.8 V
= 1.5 V
= 3.0 V
= 2.5 V
= 1.8 V
= 1.5 V
= 3.3 V
OH
OH
(Min) = 2.4 V.
(Min) = 2.0 V.
shows board design recommendations to ensure proper JTAG chain
V
v
v
v
CC IO
v
v
v
v
v
v
(1),
(1),
(1),
= 3.3 V
(1)
(1)
(1)
(1)
(1)
(1)
(4)
(4)
(4)
CCIO
Arria II GX TDO V
V
v
v
v
C CIO
levels.
v
v
v
v
v
v
(1),
(1),
(1),
= 3.0 V
(1)
(1)
(1)
(1)
(1)
(1)
(4)
(4)
(4)
C CIO
V
v
v
Voltage Level in I/O Bank 8C
CC IO
v
v
v
v
v
v
v
(2),
(2),
= 2.5 V
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(5)
(5)
chapter.
Arria II GX Device Handbook, Volume 1
V
C CIO
v
v
v
v
v
v
v
v
v
= 1.8 V
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(6)
CCIO
Level shifter
Level shifter
Level shifter
Level shifter
Level shifter
Level shifter
Level shifter
V
CC IO
required
required
required
required
required
required
required
power
= 1.5 V
v
v
IEEE
11–5
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