EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 163

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II GX Devices
Arria II GX Memory Interfaces Pin Support
Table 7–2. Number of DQ/DQS Groups and I/O Modules in Arria II GX Devices per Side (Part 2 of 2)
Figure 7–3. Number of DQ/DQS Groups per Bank in EP2AGX45 and EP2AGX65 Devices in the 358-Pin Ultra Fineline BGA
Package
Notes to
(1) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs.
(2) Several configuration pins in Bank 6A are shared with DQ/DQS pins. You cannot use a 4 DQ/DQS group with any of its pin members used for
(3) Arria II GX devices in the 358-pin Ultra FineLine BGA package do not support 36 QDR II+/QDR II SRAM interface.
© July 2010 Altera Corporation
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
Note to
(1) Each I/O module consists of 16 I/O pins. 12 of the 16 pins are DQ/DQS pins.
Device
configuration purposes. Ensure that the DQ/DQS groups you have chosen are not also used for configuration.
Figure
Table
(Note
7–2:
7–3:
780-Pin
FineLine BGA
1152-Pin
FineLine BGA
1152-Pin
FineLine BGA
1), (2),
Package
Figure 7–3
EP2AGX65 devices in the 358-pin Ultra FineLine BGA (UBGA) package.
(3)
Top/Bottom/
Right
Top/Bottom
Right
Top/Bottom/
Right
Side
shows the number of DQ/DQS groups per bank in EP2AGX45 and
22 User I/Os
22 User I/Os
×32/×36=0
×16/×18=0
×32/×36=0
I/O Bank 3A
×16/×18=0
I/O Bank 8A
×8/×9=1
×8/×9=1
and EP2AGX65 Devices in the
×4=2
×4=2
358-Pin Ultra FineLine BGA
EP2AGX45
I/O Module
Number of
(1)
12
7
9
8
38 User I/Os
I/O Bank 7A
I/O Bank 4A
38 User I/Os
×16/×18=1
×32/×36=0
×16/×18=1
×32/×36=0
×8/×9=2
×8/×9=2
×4=4
×4=4
×4
14
18
16
24
18 User I/Os
18 User I/Os
I/O Bank 5A
I/O Bank 6A
×16/×18=0
×32/×36=0
×16/×18=0
×32/×36=0
×8/×9=1
×8/×9=1
×4=2
×4=2
Number of DQ/DQS Groups
×8/×9
12
7
9
8
Arria II GX Device Handbook, Volume 1
×16/×18
3
4
4
6
×32/×36
1
2
2
2
7–5