EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 126

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–34
Figure 5–26. Scan-Chain Order of PLL Components for Arria II GX PLLs
Figure 5–27. Scan-Chain Bit-Order Sequence for Post-Scale Counters in Arria II GX PLLs
Arria II GX Device Handbook, Volume 1
DATAOUT
DATAIN
HB
LB
0
0
Table 5–10. Arria II GX PLL Reprogramming Bits (Part 2 of 2)
Figure 5–26
seven post-scale counters. The reconfiguration bits start with the C6 post-scale
counter.
Figure 5–27
Arria II GX PLLs.
Loop Filter Resistor
Unused CP/LF
Total number of bits
Notes to
(1) Includes two control bits: rbypass for bypassing the counter and rselodd to select the output clock duty
(2) LSB for C6 low-count value is the first bit shifted into the scan chain for the Left and Right PLLs.
(3) MSB for loop filter is the last bit shifted into the scan chain.
cycle.
HB
C6
LB
1
1
Table
MSB
DATAOUT
shows the scan chain order of Arria II GX PLL components which have
shows the scan-chain bit-order sequence for post-scale counters in all
5–10:
Block Name
HB
LB
LF
2
2
C5
K
HB
LB
3
3
CP
HB
C4
LB
4
4
LSB
HB
LB
5
5
C3
Counter
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
N
—
0
0
HB
LB
6
6
Number of Bits
C2
HB
LB
7
7
M
Other
—
5
7
rselodd
© July 2010 Altera Corporation
rbypass
(1)
C1
C0
PLLs in Arria II GX Devices
DATAIN
Total
180
5
7