EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 96

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–4
Clocking Regions
Figure 5–3. Arria II GX Device Dual-Regional Clock Region
Arria II GX Device Handbook, Volume 1
PLL_4
PLL_1
Arria II GX devices provide up to 64 distinct clock domains (16 GCLKs + 48 RCLKs)
in the entire device. Use these clock resources to form the following three types of
clock regions:
■
■
■
To form the entire device clock region, a source (not necessarily a clock signal) drives a
GCLK network that can be routed through the entire device. This clock region has a
higher skew when compared with other clock regions, but allows the signal to reach
every destination in the device. This is a good option for routing global reset and clear
signals or routing clocks throughout the device.
To form a regional clock region, a source drives a single-quadrant of the device. This
clock region provides the lowest skew in a quadrant and is a good option if all
destinations are in a single device quadrant.
To form a dual-regional region, a single source (a clock pin or PLL output) generates a
dual-regional clock by driving two regional clock networks (one from each quadrant).
This technique allows destinations across two device quadrants to use the same
low-skew clock. The routing of this signal on an entire side has approximately the
same delay as in a regional clock region. Internal logic can also drive a dual-regional
clock network. Corner PLL outputs generate a dual-regional clock network through
clock multiplexers that serve the two immediate quadrants of the device.
shows the dual-regional clock region.
Entire device
Regional
Dual regional
PLL_2
PLL_3
Regional clock
multiplexers
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
Clock pins or PLL outputs
can drive half of the device to
create side-wide clocking
regions for improved
interface timing.
Clock Networks in Arria II GX Devices
© July 2010 Altera Corporation
Figure 5–3