EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 151

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EP2AGX95EF29I5N

Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX95EF29I5N

Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2AGX95EF29I5N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2AGX95EF29I5N
Manufacturer:
ALTERA
0
Chapter 6: I/O Features in Arria II GX Devices
Arria II GX Termination Schemes for I/O Standards
Figure 6–9. Arria II GX Differential HSTL I/O Standard Termination
© July 2010 Altera Corporation
Termination
External
On-Board
Termination
Series
OCT
Arria II GX
Arria II GX
Series OCT
Transmitter
Transmitter
HSTL Class I
50 Ω
Figure 6–9
Arria II GX devices.
LVDS
The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power,
general-purpose I/O interface standard. In Arria II GX devices, the LVDS I/O
standard requires a 2.5-V V
LVDS requires a 100- termination resistor between the two signals at the input
buffer. Arria II GX devices provide an optional 100- differential termination resistor
in the device with R
700 Mbps.
HSTL Class I
Z
Z
50 Ω
50 Ω
0
0
= 50 Ω
= 50 Ω
50 Ω
shows the details of differential HSTL I/O standard termination on
V TT V TT
V TT
V TT
50 Ω
50 Ω
50 Ω
D
OCT. The external-resistor topology is for a data rate of up to
Receiver
Receiver
CCIO
level. The LVDS input buffer requires 2.5-V V
Arria II GX
Series OCT
Arria II GX
Transmitter
HSTL Class II
Transmitter
25 Ω
50 Ω
V TT V TT
V TT
V TT
50 Ω
50 Ω
Z
Z
0
0
50 Ω
= 50 Ω
= 50 Ω
HSTL Class II
50 Ω
50 Ω
Arria II GX Device Handbook, Volume 1
50 Ω
V TT
V TT
V TT V TT
50 Ω
50 Ω
50 Ω
Receiver
Receiver
CCPD
.
6–17

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