EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 99

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II GX Devices
Clock Networks in Arria II GX Devices
Clock Control Block
© July 2010
Altera Corporation
Table 5–6
Table 5–6. Arria II GX RCLK Outputs from PLLs
Every GCLK and RCLK network has its own clock control block. The control block
provides the following features:
■
■
■
Figure 5–4
Select the clock source for the GCLK control block either statically or dynamically. You
can either statically select the clock source with a setting in the Quartus
or you can dynamically select the clock source with an internal logic to drive the
multiplexer select inputs. When selecting the clock source dynamically, you can either
select two PLL outputs (such as C0 or C1), or a combination of clock pins or PLL
outputs.
RCLK[0..11]
RCLK[12..23]
RCLK[24..35]
RCLK[36..47]
Clock source selection (dynamic selection for GCLKs)
GCLK multiplexing
Clock power down (static or dynamic clock enable or disable)
Clock Resource
lists how the PLL clock outputs connect to RCLK networks.
and
Figure 5–5
show the GCLK and RCLK select blocks, respectively.
—
—
v
v
1
—
—
v
v
2
—
—
PLL Number
v
v
3
Arria II GX Device Handbook, Volume 1
—
—
v
v
4
—
—
—
v
®
5
II software,
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—
—
v
6
5–7