EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 297

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 11: JTAG Boundary-Scan Testing
BST Operation Control
Figure 11–2. Arria II GX HSSI Receiver/Input Clock Buffer BSC with IEEE Std. 1149.6 BST Circuitry
BST Operation Control
© July 2010
HIGHZ
SCIN SHIFT
Altera Corporation
f
0
0
1
1
Figure 11–2
For information about Arria II GX user I/O boundary-scan cells, refer to the
1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices
Table 11–1
Table 11–1. Arria II GX Boundary-Scan Register Length
Capture
D
D
CLK
Q
Q
Registers
SDOUT
UPDATE
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGX45
EP2AGX65
EP2AGX95
lists the boundary-scan register length for Arria II GX devices.
Update
shows the Arria II GX HSSI receiver/input clock buffer BSC.
Device
MODE
AC_TEST
BSRX1
BSOUT1
BSRX0
BSOUT0
MEM_INIT
AC_MODE
BSCAN
Optional INTEST/RUNBIST
PMA
Boundary-Scan Register Length
not supported
Hysteretic
Hysteretic
(DATAIN)
Memory
Memory
Mission
1,467
1,971
1,971
1,227
1,227
1,467
chapter.
Arria II GX Device Handbook, Volume 1
AC JTAG Test
AC JTAG Test
Receiver
Receiver
Rx Input
Buffer
IEEE
Pad
Pad
11–3