EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 174

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–16
Figure 7–11. DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry
Notes to
(1) For possible reference input clock pins for each DLL, refer to
(2) You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings.
Arria II GX Device Handbook, Volume 1
Figure
Phase-Shift
7–11:
Reference
Circuitry
Clock (2)
DQS
DLL
6
DQS phase-shift circuitry is connected to DQS logic blocks that control each DQS/CQ
or CQn pin. The DQS logic blocks allow the DQS delay settings to be updated
concurrently at every DQS/CQ or CQn pin.
to IOE
6
CQn
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
to IOE
CQn
Pin
Δt
DQS Logic
Blocks
to IOE
“DLL” on page
CQn
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
7–17.
to IOE
(Note 1)
CQn
Chapter 7: External Memory Interfaces in Arria II GX Devices
Pin
Δt
6
Phase-Shift
Reference
Clock (2)
Circuitry
DLL
6
DQS
IOE
IOE
IOE
IOE
to
to
to
to
Arria II GX External Memory Interface Features
DQS Logic
Blocks
© July 2010 Altera Corporation
Δt
Δt
Δt
Δt
DQS/CQ
DQS/CQ
CQn
CQn
Pin
Pin
Pin
Pin