EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 171

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II GX Devices
Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface
Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM
Interface
Rules to Combine Groups
© July 2010 Altera Corporation
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This implementation combines ×16/×18 DQ/DQS groups to interface with a ×36
QDR II+/QDR II SRAM device. The ×36 read data bus uses two ×16/×18 groups, and
the ×36 write data uses another two ×16/×18 or four ×8/×9 groups. The CQ/CQn
signal traces are split on the board trace to connect to two pairs of CQ/CQn pins in
the FPGA. This is the only connection on the board that you must change for this
implementation. Other QDR II+/QDR II SRAM interface rules for Arria II GX devices
also apply for this implementation.
The UniPHY IP core does not use the QVLD signal, so you can leave the QVLD signal
unconnected as in any QDR II+/QDR II SRAM interfaces in Arria II GX devices.
For more information about the UniPHY IP core, refer to the
Handbook.
Use one side of the device when using ×36 mode emulation interface whenever
possible, even though the ×36 group formed by a combination of DQ/DQS groups
from the top and bottom I/O banks, or top/bottom I/O bank and right I/O banks is
supported.
In 572-pin package devices, there is at most one ×16/×18 group per I/O bank. You can
combine two ×16/×18 groups from a single side of the device for a ×36 interface.
358-pin package devices have only one ×16/×18 group in each bank 4A and 7A. You
can only form a ×36 interface with these two banks.
For devices that do not have four ×16/×18 groups in a single side of the device to
form two ×36 groups for read and write data, you can form one ×36 group on one side
of the device and another ×36 group on the other side of the device. Altera
recommends forming two ×36 groups on column I/O banks (top and bottom) only,
although forming a ×36 group from column I/O banks and another ×36 group from
row I/O banks for the read and write data buses is supported. For vertical migration
with the ×36 emulation implementation, you must check if migration is possible by
enabling device migration. The Quartus II software also supports the use of four
×8/×9 DQ groups for write data pins and the migration of these groups across device
density. 358-pin package devices can only form a ×36 group for write data pin with
four ×8/×9 groups.
Arria II GX Device Handbook, Volume 1
External Memory Interface
7–13