EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 189

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
LVDS SERDES and DPA Block Diagram
Table 8–2. LVDS Channels Supported in Arria II GX Device Column I/O Banks
LVDS SERDES and DPA Block Diagram
© July 2010
Notes to
(1) There are no dedicated SERDES and DPA circuitry in device column I/O banks.
(2) RD = True LVDS input buffers with R
(3) RX = True LVDS input buffers without R
(4) TX = True LVDS output buffers.
(5) eTX = Emulated LVDS output buffers, either LVDS_E_3R or LVDS_E_1R.
(6) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins.
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGX45
EP2AGX65
EP2AGX95
Device
Table
Altera Corporation
8–2:
358-Pin FlipChip UBGA
24(RX, TX, or eTX)
24(RX, TX, or eTX)
25(RD or eTX) +
25(RD or eTX) +
The Arria II GX devices have dedicated SERDES and DPA circuitry for LVDS
transmitters and receivers on the right side of the device.
SERDES and DPA block diagram. This diagram shows the interface signals for the
transmitter and receiver datapaths. For more information, refer to
Transmitter” on page 8–7
—
—
—
—
D
OCT support.
D
OCT support.
572-Pin FlipChip FBGA
32(RX, TX, or eTX)
32(RX, TX, or eTX)
32(RX, TX, or eTX)
32(RX, TX, or eTX)
33(RD or eTX) +
33(RD or eTX) +
33(RD or eTX) +
33(RD or eTX) +
and
—
—
“Differential Receiver” on page
780-Pin FlipChip FBGA
56(RX, TX, or eTX)
56(RX, TX, or eTX)
56(RX, TX, or eTX)
56(RX, TX, or eTX)
56(RX, TX, or eTX)
56(RX, TX, or eTX)
57(RDs or eTX) +
(Note
57(RD or eTX) +
57(RD or eTX) +
57(RD or eTX) +
57(RD or eTX) +
57(RD or eTX) +
1), (2), (3), (4), (5),
Figure 8–2
Arria II GX Device Handbook, Volume 1
8–9.
“Differential
1152-Pin FlipChip FBGA
shows the LVDS
(6)
72(RX, TX, or eTX)
72(RX, TX, or eTX)
96(RX, TX, or eTX)
96(RX, TX, or eTX)
73(RD or eTX) +
73(RD or eTX) +
97(RD or eTX) +
97(RD or eTX) +
—
—
8–5