EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 50
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
- Current page: 50 of 306
- Download datasheet (7Mb)
3–10
Simple Dual-Port Mode
Table 3–4. Arria II GX M9K Block Mixed-Width Configurations
Arria II GX Device Handbook, Volume 1
8K×1
4K×2
2K×4
1K×8
512×16
256×32
1K×9
512×18
256×36
Read Port
All memory blocks support simple dual-port mode. Simple dual-port mode allows
you to perform one-read and one-write operation to different locations at the same
time.
Figure 3–11. Arria II GX Simple Dual-Port Memory
Note to
(1) Simple dual-port RAM supports input and output clock mode in addition to the read and write clock mode shown.
Simple dual-port mode supports different read and write data widths (mixed width
support).
dual-port mode. MLABs do not have native support for mixed width operations. The
Quartus II software can implement mixed width memories in MLABs with more than
one MLAB.
In simple dual-port mode, M9K blocks support separate write-enable and read-enable
signals. Read-during-write operations to the same address can either output a don’t
care value or old data.
MLABs only support a write-enable signal. Read-during-write behavior for the
MLABs can be either don’t care or old data. The available choices depend on the
configuration of the MLAB.
Figure 3–12
dual-port mode with unregistered outputs for M9K. Registering the M9K’s outputs
would simply delay the q output by one clock cycle.
8K×1
v
v
v
v
v
v
—
—
—
Figure 3–11
Figure
Table 3–4
4K×2
v
v
v
v
v
v
—
—
—
3–11:
shows timing waveforms for read and write operations in simple
shows a simple dual-port configuration.
2K×4
lists the mixed width configurations for the M9K blocks in simple
v
v
v
v
v
v
—
—
—
1K×8
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
v
v
v
v
v
v
—
—
—
512×16
Write Port
v
v
v
v
v
v
—
—
—
(Note 1)
rd_addressstall
256×32
v
v
v
v
v
v
—
—
—
rdaddress[ ]
Chapter 3: Memory Blocks in Arria II GX Devices
rdclocken
rdclock
rden
q[ ]
© November 2009 Altera Corporation
1K×9
—
—
—
—
—
—
v
v
v
512×18
—
—
—
—
—
—
v
v
v
Memory Modes
256×36
—
—
—
—
—
—
v
v
v
Related parts for EP2AGX95EF29I5N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: